The present invention generally relates to the fabrication and bonding of wafers, such as wafers for integrated circuit (IC) devices. More particularly, this invention relates to processes and bonding pad structures capable of compensating for nonplanarities in wafer surfaces.
The fabrication of MEMS (microelectromechanical systems) devices typically entails bulk micromachining, surface machining, or combinations of the two to produce a three-dimensional (3-D) sensing structure. A MEMS device is often integrated with one or more CMOS readout circuits by means of wafer-level bonding, in which the wafer on which MEMS devices have been fabricated (the “MEMS wafer”) is bonded to the wafer on which CMOS circuits have been fabricated (the “CMOS wafer”). Because of the thermal budget for CMOS circuits, low temperature metal bonding methods, including solder bonding, transient liquid phase (TLP) bonding, and eutectic bonding, are commonly used when bonding MEMS and CMOS wafers. Metal bond stacks may be formed on either or both of the MEMS and CMOS wafers, followed by heating to melt (reflow) the bond stacks and then cooling to form the metallurgical bond. In the case of eutectic bonding, bond stacks may be formed to contain the desired eutectic alloy or different metal layers that when molten will form the desired eutectic alloy. Eutectic bonding can also be achieved by interdiffusion with the substrates being bonded. As a nonlimiting example, if the substrates are silicon wafers, gold-silicon (Au—Si) eutectic bonding can be performed by depositing gold on one or both wafers, and then forming the desired Au—Si eutectic alloy (about 18.6 atomic percent Si; about 2.85 weight percent Si) by heating the wafers to cause interdiffusion of silicon from the wafers and gold from the deposited gold. The resulting Au—Si eutectic alloy melts as a result of having a lower melting temperature (about 363° C.) than either gold or silicon (about 1065° C. and about 1410° C., respectively). On cooling, the Au—Si eutectic alloy solidifies and metallurgically bonds the wafers. Au—Si eutectic bonding offers certain notable advantages, including the ability to be performed at a relatively low temperature (about 363° C.) and providing excellent sealing hermeticity, high bonding strength and good long-term stability. As a result, Au—Si eutectic bonding has found uses in various semiconductor fabrication processes, including MEMS-CMOS integration and vacuum packaging of MEMS devices.
Nonuniform metal bonding and reflow can occur if one or both wafers being bonded have a sufficient degree of curvature at their mating surfaces. The curvature of a wafer can be caused by various parameters and conditions. For example, curvature of silicon-on-insulator (SOI) wafers (widely used as device wafers for MEMS) can be induced when the MEMS structure is etched in the device layer of the wafer. While the amount of curvature tolerated by a metal bonding process will depend on various factors relating to processing conditions and packaging characteristics, it is believed that a radius of curvature of several hundred meters will typically not pose a problem during bonding, but that a radius of curvature of less than a hundred meters, for example, about sixty meters or less, may be sufficient to result in nonuniform metal bonding and reflow. As an example, in a Au—Si eutectic bonding process using a four micrometer-thick layer of plated gold, any wafer curvature resulting in a gap exceeding the thickness of the plated gold will likely result in incomplete or inadequate bonding. Though wafer curvature can be overcome to some degree by increased bonding pressure, excessive curvature will lead to reduced yields as a result of nonuniform bonding forces across the wafer interface. FIG. 1A schematically depicts a wafer stack 10 that is illustrative of this scenario. The upper wafer 12 is a device wafer whose surface 16 exhibits curvature (not to scale) as a result of processing (for example, multiple films), formation (for example, SOI), etc. As a result, a gap 20 is present within the interface 22 between the surface 16 of the device wafer 12 and the mating surface 18 of a CMOS wafer 14. FIG. 1B maps the distribution of bonding forces that may be present at bonding sites 24 between the wafers 10 and 12 if increased bonding pressure is applied in an effort to overcome wafer curvature. Light shading near the perimeter of the interface 22 denotes the presence of excessive bonding forces that can lead to metal squeeze-out and electrical shorting between electrodes, and dark shading at the center of the interface 22 denotes areas where the bonding forces do not sufficiently overcome the curvature with the result that incomplete or weak bonding will occur. The intermediate shading denotes levels of bonding forces that are more likely to result in acceptable bonds.
Because a certain degree of wafer curvature always exists due to the nature of wafer formation and/or processing, it would be desirable to minimize or eliminate the detrimental effect of wafer curvature leading to nonuniform metal bonding.